Physical Design for System-On-a-Chip

This chapter is focused on the physical design for system-on-a-chip (SOC). Physical design refers to all synthesis steps that convert a circuit representation (gates, transistors) into a geometric representation (polygons and theirs shapes). See Figure 1 for an illustration. The geometric representation, also called layout , is used to design masks and then manufacture a chip. As a very complicated design process, modern physical design is typically divided into three major steps: floorplanning , placement , and routing. Floorplanning is an essential design step for hierarchical, building block design methodology. Given a set of hard blocks (whose shapes cannot be changed) and/or soft blocks (whose shapes can be adjusted) and a netlist, floorplanning determine the shapes of soft blocks and assemble the blocks into a rectangle (chip) such that a predefined cost metric (such as the chip area, wirelength, wire congestion) is optimized. Placement is the process of assigning the circuit components into a chip region. It can be considered as a restricted floorplanning problem for hard blocks with some dimension similarity. Following placement, the routing process defines the precise paths for conductors that carry electrical signals on the chip layout to interconnect all pins that are electrically equivalent. After routing, some physical verification processes (such as design rule checking (DRC), performance checking, and reliability checking) are performed to verify if all geometric patterns, circuit timing, and electrical effects satisfy the design rules and specifications.